synquacer: Enable MMU using xlat_tables_v2 library

BL31 runs from SRAM which is a non-coherent memory on synquacer. So
enable MMU with SRAM memory marked as Non-Cacheable and mark page tables
kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables
for Device address space.

Signed-off-by: Sumit Garg <[email protected]>

diff --git a/plat/socionext/synquacer/include/platform_def.h b/plat/socionext/synquacer/include/platform_def.h
index 82c38109ed7c38c1afb544e01867a4106a907a6a..aa15234f53792ce200aaa5e00fac1e7a64df1b19 100644 (file)
--- a/plat/socionext/synquacer/include/platform_def.h
+++ b/plat/socionext/synquacer/include/platform_def.h
@@ -18,6 +18,11 @@
 #define CACHE_WRITEBACK_SHIFT          6
 #define CACHE_WRITEBACK_GRANULE                (1 << CACHE_WRITEBACK_SHIFT)
 
+#define PLAT_PHY_ADDR_SPACE_SIZE       (1ULL << 32)
+#define PLAT_VIRT_ADDR_SPACE_SIZE      (1ULL << 32)
+#define MAX_XLAT_TABLES                        4
+#define MAX_MMAP_REGIONS               6
+
 #define PLATFORM_STACK_SIZE            0x400
 
 #define BL31_BASE                      0x04000000

diff --git a/plat/socionext/synquacer/include/sq_common.h b/plat/socionext/synquacer/include/sq_common.h
index b72dfa7fe9fae2a6ce76fd9d5f17e1b1da336dce..b9600f02ca0d8f5e30d5ad2edec6ad1dc41051c3 100644 (file)
--- a/plat/socionext/synquacer/include/sq_common.h
+++ b/plat/socionext/synquacer/include/sq_common.h
@@ -8,6 +8,7 @@
 #define __SQ_COMMON_H__
 
 #include <sys/types.h>
+#include <xlat_tables_v2.h>
 
 void plat_sq_interconnect_init(void);
 void plat_sq_interconnect_enter_coherency(void);
@@ -21,4 +22,7 @@ void sq_gic_cpuif_enable(void);
 void sq_gic_cpuif_disable(void);
 void sq_gic_pcpu_init(void);
 
+void sq_mmap_setup(uintptr_t total_base, size_t total_size,
+                  const struct mmap_region *mmap);
+
 #endif /* __SQ_COMMON_H__ */

diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c
index d2a458ce3ac16de65e6969f3dc06994a4599906a..1d3d3b6142d54d42da773835d9fa817d2ebf73bd 100644 (file)
--- a/plat/socionext/synquacer/sq_bl31_setup.c
+++ b/plat/socionext/synquacer/sq_bl31_setup.c
@@ -133,6 +133,13 @@ void bl31_plat_runtime_setup(void)
 
 void bl31_plat_arch_setup(void)
 {
+       sq_mmap_setup(BL31_BASE, BL31_SIZE, NULL);
+       enable_mmu_el3(XLAT_TABLE_NC);
+}
+
+void bl31_plat_enable_mmu(uint32_t flags)
+{
+       enable_mmu_el3(flags | XLAT_TABLE_NC);
 }
 
 unsigned int plat_get_syscnt_freq2(void)

diff --git a/plat/socionext/synquacer/sq_xlat_setup.c b/plat/socionext/synquacer/sq_xlat_setup.c
new file mode 100644 (file)
index 0000000..ae14700
--- /dev/null
+++ b/plat/socionext/synquacer/sq_xlat_setup.c
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <platform_def.h>
+#include <xlat_tables_v2.h>
+
+#define SQ_REG_REGION_BASE     0x20000000ULL
+#define SQ_REG_REGION_SIZE     0x60000000ULL
+
+void sq_mmap_setup(uintptr_t total_base, size_t total_size,
+                        const struct mmap_region *mmap)
+{
+       VERBOSE("Trusted RAM seen by this BL image: %p - %p\n",
+               (void *)total_base, (void *)(total_base + total_size));
+       mmap_add_region(total_base, total_base,
+                       total_size,
+                       MT_NON_CACHEABLE | MT_RW | MT_SECURE);
+
+       /* remap the code section */
+       VERBOSE("Code region: %p - %p\n",
+               (void *)BL_CODE_BASE, (void *)BL_CODE_END);
+       mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
+                       round_up(BL_CODE_END, PAGE_SIZE) - BL_CODE_BASE,
+                       MT_NON_CACHEABLE | MT_RO | MT_SECURE);
+
+       /* Re-map the read-only data section */
+       VERBOSE("Read-only data region: %p - %p\n",
+               (void *)BL_RO_DATA_BASE, (void *)BL_RO_DATA_END);
+       mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE,
+                       round_up(BL_RO_DATA_END, PAGE_SIZE) - BL_RO_DATA_BASE,
+                       (MT_NON_CACHEABLE | MT_RO | MT_EXECUTE_NEVER |
+                        MT_SECURE));
+
+       /* remap the coherent memory region */
+       VERBOSE("Coherent region: %p - %p\n",
+               (void *)BL_COHERENT_RAM_BASE, (void *)BL_COHERENT_RAM_END);
+       mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
+                       BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE,
+                       MT_DEVICE | MT_RW | MT_SECURE);
+
+       /* register region */
+       mmap_add_region(SQ_REG_REGION_BASE, SQ_REG_REGION_BASE,
+                       SQ_REG_REGION_SIZE,
+                       MT_DEVICE | MT_RW | MT_SECURE);
+
+       /* additional regions if needed */
+       if (mmap)
+               mmap_add(mmap);
+
+       init_xlat_tables();
+}